forked from github/verilator
25 lines
575 B
Systemverilog
25 lines
575 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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int val1, val2;
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always @val1 $write("[%0t] val1=%0d val2=%0d\n", $time, val1, val2);
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assign #10 val2 = val1;
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initial begin
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val1 = 1;
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#10 val1 = 2;
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fork #5 val1 = 3; join_none
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val1 = #10 val1 + 2;
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val1 <= #10 val1 + 2;
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fork #5 val1 = 5; join_none
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#20 $write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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