forked from github/verilator
67 lines
1.4 KiB
Coq
67 lines
1.4 KiB
Coq
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// $Id:$
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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module t_loop (/*AUTOARG*/
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// Outputs
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passed,
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// Inputs
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clk
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);
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input clk;
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output passed; reg passed; initial passed = 0;
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reg [7:0] cyc; initial cyc=0;
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reg [31:0] loops;
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reg [31:0] loops2;
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integer i;
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always @ (posedge clk) begin
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cyc <= cyc+8'd1;
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if (cyc == 8'd1) begin
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$write("[%0t] t_loop: Running\n",$time);
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// Unwind <
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loops = 0;
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loops2 = 0;
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for (i=0; i<16; i=i+1) begin
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loops = loops + i; // surefire lint_off_line ASWEMB
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loops2 = loops2 + i; // surefire lint_off_line ASWEMB
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end
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if (i !== 16) $stop;
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if (loops !== 120) $stop;
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if (loops2 !== 120) $stop;
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// Unwind <=
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loops = 0;
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for (i=0; i<=16; i=i+1) begin
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loops = loops + 1;
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end
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if (i !== 17) $stop;
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if (loops !== 17) $stop;
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// Don't unwind breaked loops
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loops = 0;
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for (i=0; i<16; i=i+1) begin
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loops = loops + 1;
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if (i==7) i=99; // break out of loop
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end
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if (loops !== 8) $stop;
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// Don't unwind large loops!
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loops = 0;
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for (i=0; i<100000; i=i+1) begin
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loops = loops + 1;
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end
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if (loops !== 100000) $stop;
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//
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$write("[%0t] t_loop: Passed\n",$time);
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passed <= 1'b1;
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end
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end
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endmodule
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// Local Variables:
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// compile-command: "./vlint __FILE__"
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// End:
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