forked from github/verilator
21 lines
638 B
Perl
21 lines
638 B
Perl
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
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# $Id$
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# General Public License or the Perl Artistic License.
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compile (
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fails=>$Last_Self->{v3},
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expect=>
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'%Warning-VARHIDDEN: t/t_var_bad_hide.v:\d+: Declaration of signal hides declaration in upper scope: top
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.*
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%Warning-VARHIDDEN: t/t_var_bad_hide.v:\d+: ... Location of original declaration
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%Error: Exiting due to.*',
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);
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ok(1);
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1;
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