	// verilator_coverage annotation
	// DESCRIPTION: Verilator: Verilog Test module
	//
	// This file ONLY is placed under the Creative Commons Public Domain, for
	// any use, without warranty, 2008 by Wilson Snyder.
	// SPDX-License-Identifier: CC0-1.0
	
	module t (/*AUTOARG*/
	   // Inputs
	   clk
	   );
	
	   input clk;
	
	   reg   toggle;
%000002	   initial toggle=0;
	
	   integer cyc;
%000002	   initial cyc=1;
	
	   wire [7:0] cyc_copy = cyc[7:0];
	
	   alpha a1 (/*AUTOINST*/
	             // Inputs
	             .clk                       (clk),
	             .toggle                    (toggle));
	   alpha a2 (/*AUTOINST*/
	             // Inputs
	             .clk                       (clk),
	             .toggle                    (toggle));
	   beta  b1 (/*AUTOINST*/
	             // Inputs
	             .clk                       (clk),
	             .toggle                    (toggle));
	   beta  b2 (/*AUTOINST*/
	             // Inputs
	             .clk                       (clk),
	             .toggle                    (toggle));
	   tsk   t1 (/*AUTOINST*/
	             // Inputs
	             .clk                       (clk),
	             .toggle                    (toggle));
	   off   o1 (/*AUTOINST*/
	             // Inputs
	             .clk                       (clk),
	             .toggle                    (toggle));
	
 000020	   always @ (posedge clk) begin
 000020	      if (cyc!=0) begin
%000000	      verilator_coverage: (next point on previous line)

 000010	         cyc <= cyc + 1;
 000010	         toggle <= '0;
	         // Single and multiline if
%000002	         if (cyc==3) $write("");
%000009	         verilator_coverage: (next point on previous line)

%000002	         if (cyc==3)
%000009	         verilator_coverage: (next point on previous line)

%000001	           begin
%000001	              $write("");
	           end
	         // Single and multiline else
%000002	         if (cyc==3) ; else $write("");
%000018	         verilator_coverage: (next point on previous line)

%000002	         if (cyc==3) ;
%000009	         verilator_coverage: (next point on previous line)

	         else
%000009	           begin
%000009	              $write("");
	           end
	         // Single and multiline if else
%000002	         if (cyc==3) $write(""); else $write("");
%000018	         verilator_coverage: (next point on previous line)

%000002	         if (cyc==3)
%000009	         verilator_coverage: (next point on previous line)

%000001	           begin
%000001	              $write("");
	           end
	         else
%000009	           begin
%000009	              $write("");
	           end
	         //  multiline elseif
%000002	         if (cyc==3)
%000001	           begin
%000001	              $write("");
	           end
%000002	         else if (cyc==4)
%000001	           begin
%000001	              $write("");
	           end
%000002	         else if (cyc==5)
%000007	         verilator_coverage: (next point on previous line)

%000001	           begin
%000001	              $write("");
	           end
	         else
%000007	           begin
%000007	              $write("");
	           end
	         // Single and multiline while
%000000	         while (0);
%000000	         while (0) begin
%000000	            $write("");
	         end
%000000	         do ; while (0);
 000010	         do begin
%000000	         verilator_coverage: (next point on previous line)

 000010	            $write("");
%000000	            verilator_coverage: (next point on previous line)

%000000	         end while (0);
	         //===
	         // Task and complicated
%000002	         if (cyc==3) begin
%000001	            toggle <= '1;
	         end
%000002	         else if (cyc==5) begin
	`ifdef VERILATOR
%000001	            $c("this->call_task();");
	`else
	            call_task();
	`endif
	         end
%000002	         else if (cyc==10) begin
%000007	         verilator_coverage: (next point on previous line)

%000001	            $write("*-* All Finished *-*\n");
%000001	            $finish;
	         end
	      end
	   end
	
%000002	   task call_task;
	      /* verilator public */
%000001	      t1.center_task(1'b1);
	   endtask
	
	endmodule
	
	module alpha (/*AUTOARG*/
	   // Inputs
	   clk, toggle
	   );
	   input clk;
	   input toggle;
 000040	   always @ (posedge clk) begin
%000004	      if (toggle) begin  // CHECK_COVER(0,"top.t.a*",2)
 000018	      verilator_coverage: (next point on previous line)

%000002	         $write("");
	         // t.a1 and t.a2 collapse to a count of 2
	      end
 000018	      if (toggle) begin
	         $write("");  // CHECK_COVER_MISSING(0)
	         // This doesn't even get added
	`ifdef ATTRIBUTE
	         // verilator coverage_block_off
	`endif
	      end
	   end
	endmodule
	
	module beta (/*AUTOARG*/
	   // Inputs
	   clk, toggle
	   );
	   input clk;
	   input toggle;
	
	   /* verilator public_module */
	
 000040	   always @ (posedge clk) begin
 000020	      $write("");  // Always covered
%000000	      if (0) begin  // CHECK_COVER(0,"top.t.b*",0)
 000020	      verilator_coverage: (next point on previous line)

	         // Make sure that we don't optimize away zero buckets
%000000	         $write("");
	      end
%000004	      if (toggle) begin  // CHECK_COVER(0,"top.t.b*",2)
 000018	      verilator_coverage: (next point on previous line)

	         // t.b1 and t.b2 collapse to a count of 2
%000002	         $write("");
	      end
 000018	      if (toggle) begin : block
	         // This doesn't
	`ifdef ATTRIBUTE
	         // verilator coverage_block_off
	`endif
	         begin end  // Needed for .vlt to attach coverage_block_off
	         if (1) begin end  // CHECK_COVER_MISSING(0)
	         $write("");  // CHECK_COVER_MISSING(0)
	      end
	   end
	endmodule
	
	module tsk (/*AUTOARG*/
	   // Inputs
	   clk, toggle
	   );
	   input clk;
	   input toggle;
	
	   /* verilator public_module */
	
 000020	   always @ (posedge clk) begin
 000010	      center_task(1'b0);
	   end
	
 000022	   task center_task;
	      input external;
 000011	      begin
%000002	         if (toggle) begin  // CHECK_COVER(0,"top.t.t1",1)
 000010	         verilator_coverage: (next point on previous line)

%000001	            $write("");
	         end
%000002	         if (external) begin  // CHECK_COVER(0,"top.t.t1",1)
 000010	         verilator_coverage: (next point on previous line)

%000001	            $write("[%0t] Got external pulse\n", $time);
	         end
	      end
	   endtask
	
	endmodule
	
	module off (/*AUTOARG*/
	   // Inputs
	   clk, toggle
	   );
	   input clk;
	   input toggle;
	
	   // verilator coverage_off
	   always @ (posedge clk) begin
	      if (toggle) begin
	         $write("");  // CHECK_COVER_MISSING(0)
	         // because under coverage_module_off
	      end
	   end
	   // verilator coverage_on
 000020	   always @ (posedge clk) begin
%000002	      if (toggle) begin
%000009	      verilator_coverage: (next point on previous line)

	         // because under coverage_module_off
%000001	         $write("");
%000000	         if (0) ;  // CHECK_COVER(0,"top.t.o1",1)
%000001	         verilator_coverage: (next point on previous line)

	      end
	   end
	
	endmodule
	
