<?xml version="1.0" ?>
<!-- DESCRIPTION: Verilator output: XML representation of netlist -->
<verilator_xml>
  <files>
    <file id="a" filename="&lt;built-in&gt;" language="1800-2017"/>
    <file id="b" filename="&lt;command-line&gt;" language="1800-2017"/>
    <file id="c" filename="input.vc" language="1800-2017"/>
    <file id="d" filename="t/t_xml_first.v" language="1800-2017"/>
  </files>
  <module_files>
    <file id="d" filename="t/t_xml_first.v" language="1800-2017"/>
  </module_files>
  <cells>
    <cell fl="d6" name="t" submodname="t" hier="t">
      <cell fl="d19" name="cell1" submodname="mod1__W4" hier="t.cell1"/>
      <cell fl="d24" name="cell2" submodname="mod2" hier="t.cell2"/>
    </cell>
  </cells>
  <netlist>
    <module fl="d6" name="t" origName="t" topModule="1">
      <var fl="d12" name="clk" dtype_id="1" dir="input" vartype="logic" origName="clk"/>
      <var fl="d13" name="d" dtype_id="2" dir="input" vartype="logic" origName="d"/>
      <var fl="d14" name="q" dtype_id="2" dir="output" vartype="logic" origName="q"/>
      <var fl="d16" name="between" dtype_id="2" vartype="logic" origName="between"/>
      <instance fl="d19" name="cell1" defName="mod1__W4" origName="cell1">
        <port fl="d19" name="q" direction="out" portIndex="1">
          <varref fl="d19" name="between" dtype_id="2"/>
        </port>
        <port fl="d20" name="clk" direction="in" portIndex="2">
          <varref fl="d20" name="clk" dtype_id="1"/>
        </port>
        <port fl="d21" name="d" direction="in" portIndex="3">
          <varref fl="d21" name="d" dtype_id="2"/>
        </port>
      </instance>
      <instance fl="d24" name="cell2" defName="mod2" origName="cell2">
        <port fl="d24" name="d" direction="in" portIndex="1">
          <varref fl="d24" name="between" dtype_id="2"/>
        </port>
        <port fl="d25" name="q" direction="out" portIndex="2">
          <varref fl="d25" name="q" dtype_id="2"/>
        </port>
        <port fl="d26" name="clk" direction="in" portIndex="3">
          <varref fl="d26" name="clk" dtype_id="1"/>
        </port>
      </instance>
    </module>
    <module fl="d30" name="mod1__W4" origName="mod1">
      <var fl="d31" name="WIDTH" dtype_id="3" vartype="logic" origName="WIDTH" param="true">
        <const fl="d18" name="32&apos;sh4" dtype_id="3"/>
      </var>
      <var fl="d33" name="clk" dtype_id="1" dir="input" vartype="logic" origName="clk"/>
      <var fl="d34" name="d" dtype_id="2" dir="input" vartype="logic" origName="d"/>
      <var fl="d35" name="q" dtype_id="2" dir="output" vartype="logic" origName="q"/>
      <var fl="d38" name="IGNORED" dtype_id="3" vartype="logic" origName="IGNORED" localparam="true">
        <const fl="d38" name="32&apos;sh1" dtype_id="3"/>
      </var>
      <always fl="d40">
        <sentree fl="d40">
          <senitem fl="d40" edgeType="POS">
            <varref fl="d40" name="clk" dtype_id="1"/>
          </senitem>
        </sentree>
        <assigndly fl="d41" dtype_id="2">
          <varref fl="d41" name="d" dtype_id="2"/>
          <varref fl="d41" name="q" dtype_id="2"/>
        </assigndly>
      </always>
    </module>
    <module fl="d45" name="mod2" origName="mod2">
      <var fl="d47" name="clk" dtype_id="1" dir="input" vartype="logic" origName="clk"/>
      <var fl="d48" name="d" dtype_id="2" dir="input" vartype="logic" origName="d"/>
      <var fl="d49" name="q" dtype_id="2" dir="output" vartype="logic" origName="q"/>
      <contassign fl="d52" dtype_id="2">
        <varref fl="d52" name="d" dtype_id="2"/>
        <varref fl="d52" name="q" dtype_id="2"/>
      </contassign>
    </module>
    <typetable fl="a0">
      <basicdtype fl="d47" id="1" name="logic"/>
      <basicdtype fl="d13" id="2" name="logic" left="3" right="0"/>
      <basicdtype fl="d18" id="3" name="logic" left="31" right="0"/>
    </typetable>
  </netlist>
</verilator_xml>
