First draft of Specs and some minor updates

CALL.md

@@ -1,11 +1,11 @@
 
 ## 2023 SSCS “PICO” Open-Source Chipathon
-### – Submission deadline: May 1, 2023 – 
+### – Submission deadline: May 1, 2023 –
 
-The IEEE Solid-State Circuits Society is pleased to announce its third open-source integrated circuit (IC) design contest under the umbrella of its [PICO](https://sscs.ieee.org/about/solid-state-circuits-directions/sscs-pico-program) Program (Platform for IC Design Outreach). While this contest is open to any individual or team, we encourage the participation of pre-college students, undergraduates, and geographical regions that are underrepresented within the IC design community. 
+The IEEE Solid-State Circuits Society is pleased to announce its third open-source integrated circuit (IC) design contest under the umbrella of its [PICO](https://sscs.ieee.org/about/solid-state-circuits-directions/sscs-pico-program) Program (Platform for IC Design Outreach). While this contest is open to any individual or team, we encourage the participation of pre-college students, undergraduates, and geographical regions that are underrepresented within the IC design community.
 
 The goal of this chipathon is to bring together IC design newbies, enthusiasts and experienced mentors to benefit from the collaboration opportunities enabled by the rapidly growing open-source IC design movement. In contrast to previous chipathon editions (which were open-ended), this year’s goal is to create a specific set of building blocks that can be re-used to benefit the community as a whole.
 
 The design target (depicted in the graphic below) is a “lab bench on a chip” system that can be used to characterize basic analog circuit blocks through oscilloscope and waveform generator functionality. Participants are requested to submit innovative ideas on how these blocks should be implemented. A jury will select the best proposals (submitted as Jupyter notebooks) to assemble a collection of teams that will work together toward tapeout. We anticipate tapeouts of several candidate designs toward the end of the year, targeting GlobalFoundries’ [GF180MCU technology](https://gf180mcu-pdk.readthedocs.io/en/latest/).
 
-<img src="overview.png" width="400"/>
+<img src="figures/overview.png" width="400"/>

README.md

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 # SSCS “PICO” Open-Source Chipathon
 
-<img align="left" width="400" src="overview.png" width="450"/>
+<img align="left" width="400" src="figures/overview.png" width="450"/>
 
 
 

SPECS.md

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+# Specifications
+
+The purpose of this page is to seed some ideas on what the  “lab bench on a chip” target design may look like. Further teamwork and thinking is required to turn this into a workable design that we can tape out toward the end of the year. Each participating team may choose to work on one or more of the six building blocks identified in the diagram below. The proposals submitted by each team (in the form of Jupyter notebook) should describe in detail how you want to implement your chosen block(s), what the specifications will be, and in addition provide convincing calculations and simulation results. Layouts are not required at the proposal stage.
+
+<img src="figures/block_diagram.png" width="500"/>    
+
+To our knowledge, there aren't any published prior-art designs that we can build on. However, we can draw some inspiration from a similar system that was designed for discrete circuits. The [Analog Discovery 2](https://digilent.com/reference/test-and-measurement/analog-discovery-2/start) is a multifunction instrument that has all the functionality we are looking for (and more) and comes with detailed [schematics](https://digilent.com/reference/test-and-measurement/analog-discovery-2/hardware-design-guide). While this documentation provides a first-order idea on what we should build, the circuit design style will be somewhat different for on-chip circuitry. Additionally, it will be difficult to match all specifications within a reasonable area budget and given the 180 nm technology that we have at our disposal.
+
+What follows below are initial thoughts and minimum specs for each one of our major system components. All teams are encouraged to exceed the minimum requirements and explore what is possible!
+
+**1. Scope MUX and signal conditioning**  
+The oscilloscope design should have an input MUX that allows the macro's user to switch the ADC to a number of different test points within the DUT. It is desirable to have the MUX work for rail-to-rail inputs. The signal conditioning circuitry should have a small input capacitance and essentially "infinite" input resistance. On the output side, there must be significant drive strength to handle the high-speed ADCs and deal with their charge kickback (if applicable). A plus for signal conditioning block would be to include transimpedance stages for current measurements.
+
+| Specification | Symbol | Baseline requirement | Comment |
+| ------------- | ------ |--------------------- |-------- |
+| Scope input capacitance | Cin | <5pF | From each diff. input to ground
+| Number of differential input channels   | N  |  >=8
+| Noise   | Neq  |  <0.5 LSBrms | Contribution of the front-end to the ADC's sampled noise
 
 
-https://digilent.com/reference/test-and-measurement/analog-discovery-2/start
+**2. AWG MUX and signal conditioning**  
 
-https://digilent.com/reference/test-and-measurement/analog-discovery-2/hardware-design-guide
+**3. Clock generator**  
 
+**4. ADCs**  
+
+**5. DACs**  
+
+**6. Digital interface**  
+One of the primary goals here is to enable a convenient USB interface to a host computer. Teams working on this aspect should design both the on- and off-chip digital circuitry. For the off-chip board, we can consider the lowest cost boards from [Digilent](https://digilent.com/shop/boards-and-components/system-boards/introductory-boards/?sort=priceasc). The USB UART provided [here](https://github.com/ricynlee/cmod-a7-uart-sram-test) could be useful for establishing the communication.

diagrams/README.md

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-

figures/block_diagram.drawio

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