91 lines
1.8 KiB
Systemverilog
91 lines
1.8 KiB
Systemverilog
module SAR_SIM( );
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localparam N_bits = 8 ;
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reg clk_sar ;
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reg reset ;
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wire EOC ;
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wire [N_bits +1 : 0 ] shift_register_out ;
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Sequencer_Register #(N_bits) seq_sim (
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.clk_sar(clk_sar) ,
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.rst(reset),
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.EOC(EOC),
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.shift_register_out(shift_register_out)
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);
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reg comparator_out ;
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wire [N_bits -1 : 0]data_register_out ;
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Code_Register #(N_bits) Code_sim (
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.comparator_out(comparator_out),
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.rst(reset),
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.shift_register_out(shift_register_out),
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.data_register_out(data_register_out)
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);
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//CLK sample y CLK sar
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always #1 clk_sar = ~clk_sar ;
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wire [N_bits-1 : 0] Vin ;
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wire [N_bits-1 : 0] Vdac ;
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assign Vin = 'd5 ;
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assign Vdac = {data_register_out[0 ] , data_register_out[ 1] , data_register_out[2 ] , data_register_out[ 3] , data_register_out[ 4] , data_register_out[ 5] , data_register_out[ 6] , data_register_out[ 7]} ;
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always @(*) begin
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if(Vin >= Vdac )
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comparator_out = 'd1 ;
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else
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comparator_out = 'd0 ;
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end
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always @(*) begin
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if (EOC) begin
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reset = 'd1 ;
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#1
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reset = 'd0 ;
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end
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end
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initial begin
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clk_sar = 0 ;
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reset = 1 ;
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#2
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reset = 0 ;
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#100
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$finish ;
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end
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initial begin
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$dumpfile("Code_Reg_Out.txt") ;
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$dumpvars(0);
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end
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integer f , i ;
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initial begin
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f = $fopen("output.csv", "w");
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$fwrite(f, "clk_sar,reset,Vdac_b0,Vdac_b1,Vdac_b2,Vdac_b3,Vdac_b4,Vdac_b5,Vdac_b6,Vdac_b7\n");
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for (i=0; i<102; i++) begin
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//$fwrite(f, "%d,%d,%d,%d,%d,%d,%d\n", clk_sar , reset ,Vdac , Vin ,shift_register_out , data_register_out , comparator_out );
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$fwrite(f, "%d,%d,%d,%d,%d,%d,%d,%d,%d,%d\n", clk_sar,reset,Vdac[0],Vdac[1],Vdac[2],Vdac[3],Vdac[4],Vdac[5],Vdac[6],Vdac[7] );
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#1;
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end
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$fclose(f) ;
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$finish ;
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end
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endmodule
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