module SAR_SIM( );

localparam N_bits = 8 ;
reg clk_sar ;
reg reset ;
wire EOC ;
wire [N_bits +1 : 0 ] shift_register_out  ;

Sequencer_Register  #(N_bits) seq_sim (
    .clk_sar(clk_sar) , 
    .rst(reset),
    .EOC(EOC),
    .shift_register_out(shift_register_out) 
);

reg comparator_out ;
wire [N_bits -1 : 0]data_register_out ;

Code_Register #(N_bits) Code_sim (
        .comparator_out(comparator_out),
         .rst(reset), 
        .shift_register_out(shift_register_out),
        .data_register_out(data_register_out)
    );

//CLK sample y CLK sar
always  #1 clk_sar = ~clk_sar ; 





wire [N_bits-1 : 0] Vin ; 
wire [N_bits-1 : 0] Vdac ; 
assign Vin = 'd5 ; 

assign Vdac = {data_register_out[0 ] , data_register_out[ 1] , data_register_out[2 ] , data_register_out[ 3] , data_register_out[ 4] , data_register_out[ 5] , data_register_out[ 6] , data_register_out[ 7]} ;

always @(*) begin
    if(Vin >= Vdac )
        comparator_out = 'd1 ;
    else
         comparator_out = 'd0 ;

end

always @(*) begin
    if (EOC) begin
        reset = 'd1 ;
        #1
        reset = 'd0 ;
    end

end


initial begin
    clk_sar = 0 ;
    reset = 1 ; 

    #2
    reset = 0 ;

    #100
    $finish ;

end


initial begin 
    $dumpfile("Code_Reg_Out.txt") ; 
    $dumpvars(0); 

end 

integer  f , i ;
initial begin
    f = $fopen("output.csv", "w");
    $fwrite(f, "clk_sar,reset,Vdac_b0,Vdac_b1,Vdac_b2,Vdac_b3,Vdac_b4,Vdac_b5,Vdac_b6,Vdac_b7\n");
    for (i=0; i<102; i++) begin 
        //$fwrite(f, "%d,%d,%d,%d,%d,%d,%d\n", clk_sar , reset ,Vdac , Vin ,shift_register_out , data_register_out , comparator_out );
        $fwrite(f, "%d,%d,%d,%d,%d,%d,%d,%d,%d,%d\n", clk_sar,reset,Vdac[0],Vdac[1],Vdac[2],Vdac[3],Vdac[4],Vdac[5],Vdac[6],Vdac[7] );
        #1; 
    end
    $fclose(f) ;
    $finish ;
end


endmodule