From c46b49af0c0bffd963044975b9c36500ce66a6fe Mon Sep 17 00:00:00 2001 From: Mario1159 Date: Sat, 29 Apr 2023 16:51:50 -0400 Subject: [PATCH 1/3] Add background to ADC svg --- figures/adc.svg | 616 ++++++++++++++++++++++++++++-------------------- 1 file changed, 363 insertions(+), 253 deletions(-) diff --git a/figures/adc.svg b/figures/adc.svg index 87904aa..7411f08 100644 --- a/figures/adc.svg +++ b/figures/adc.svg @@ -1,254 +1,364 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -V -+ - - - -V -− - - - - -S&H - - - - - - - - - - -S&H - - - - - - - - - - -DAC - - - - - - - - - - - - -D -1 - - - - - - - - - - -D -2 - - - - - - - - - - -D -3 -... - - - - - - - - - - -D -12 - - - - - - - - - -V -ref - - -DAC - - - - - - - - - - - - -D -1 - - - - - - - - - - -D -2 - - - - - - - - - - -D -3 -... - - - - - - - - - - -D -12 - - -V -ref - - - - - - - - - -− -+ - - - - -SAR - -CLK -RST - - - - - - - - - - -12 -V -out - + + + + + + + + + + V + + + + + + + + + + V + + + − + + + + + + + S&H + + + + + + + + + + + + + S&H + + + + + + + + + + + + + + D + + + A + + + C + + + + + + + + + + + + + + + + D + + + 1 + + + + + + + + + + + + + D + + + 2 + + + + + + + + + + + + + D + + + 3 + + + + . + + + . + + + . + + + + + + + + + + + + + + D + + + 12 + + + + + + + + + + + + V + + + + r + + + ef + + + + + + + D + + + A + + + C + + + + + + + + + + + + + + + + D + + + 1 + + + + + + + + + + + + + D + + + 2 + + + + + + + + + + + + + D + + + 3 + + + + . + + + . + + + . + + + + + + + + + + + + + + D + + + 12 + + + + + V + + + + r + + + ef + + + + + + + + + + + + + − + + + + + + + + + + + SAR + + + + CLK + + + RST + + + + + + + + + + + + + 12 + + + V + + + out + + \ No newline at end of file From 5564587876fda2f3875a6890c18f2fd1606a6e1e Mon Sep 17 00:00:00 2001 From: Mario1159 Date: Sat, 29 Apr 2023 16:56:01 -0400 Subject: [PATCH 2/3] Add SAR data --- data/sar/output.csv | 51 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 data/sar/output.csv diff --git a/data/sar/output.csv b/data/sar/output.csv new file mode 100644 index 0000000..69578bd --- /dev/null +++ b/data/sar/output.csv @@ -0,0 +1,51 @@ +clk_sar,reset,Vdac_b0,Vdac_b1,Vdac_b2,Vdac_b3,Vdac_b4,Vdac_b5,Vdac_b6,Vdac_b7 +0,1,x,x,x,x,x,x,x,x +1,1,0,0,0,0,0,0,0,0 +0,0,0,0,0,0,0,0,0,0 +1,0,0,0,0,0,0,0,0,0 +0,0,0,0,0,0,0,0,0,1 +1,0,0,0,0,0,0,0,0,1 +0,0,0,0,0,0,0,0,1,0 +1,0,0,0,0,0,0,0,1,0 +0,0,0,0,0,0,0,1,0,0 +1,0,0,0,0,0,0,1,0,0 +0,0,0,0,0,0,1,0,0,0 +1,0,0,0,0,0,1,0,0,0 +0,0,0,0,0,1,0,0,0,0 +1,0,0,0,0,1,0,0,0,0 +0,0,0,0,1,0,0,0,0,0 +1,0,0,0,1,0,0,0,0,0 +0,0,0,1,1,0,0,0,0,0 +1,0,0,1,1,0,0,0,0,0 +0,0,1,0,1,0,0,0,0,0 +1,0,1,0,1,0,0,0,0,0 +0,0,1,0,1,0,0,0,0,0 +1,0,1,0,1,0,0,0,0,0 +0,0,0,0,0,0,0,0,0,0 +1,0,0,0,0,0,0,0,0,0 +0,0,0,0,0,0,0,0,0,1 +1,0,0,0,0,0,0,0,0,1 +0,0,0,0,0,0,0,0,1,0 +1,0,0,0,0,0,0,0,1,0 +0,0,0,0,0,0,0,1,0,0 +1,0,0,0,0,0,0,1,0,0 +0,0,0,0,0,0,1,0,0,0 +1,0,0,0,0,0,1,0,0,0 +0,0,0,0,0,1,0,0,0,0 +1,0,0,0,0,1,0,0,0,0 +0,0,0,0,1,0,0,0,0,0 +1,0,0,0,1,0,0,0,0,0 +0,0,0,1,1,0,0,0,0,0 +1,0,0,1,1,0,0,0,0,0 +0,0,1,0,1,0,0,0,0,0 +1,0,1,0,1,0,0,0,0,0 +0,0,1,0,1,0,0,0,0,0 +1,0,1,0,1,0,0,0,0,0 +0,0,0,0,0,0,0,0,0,0 +1,0,0,0,0,0,0,0,0,0 +0,0,0,0,0,0,0,0,0,1 +1,0,0,0,0,0,0,0,0,1 +0,0,0,0,0,0,0,0,1,0 +1,0,0,0,0,0,0,0,1,0 +0,0,0,0,0,0,0,1,0,0 +1,0,0,0,0,0,0,1,0,0 From 4d9b65ce5fe12c42d1344c2dd4921f7957b5befa Mon Sep 17 00:00:00 2001 From: Mario Romero Date: Sat, 29 Apr 2023 17:17:06 +0000 Subject: [PATCH 3/3] Merge manually proposal (fix path) --- spice/cdac.spice | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/spice/cdac.spice b/spice/cdac.spice index c5f0999..910c377 100644 --- a/spice/cdac.spice +++ b/spice/cdac.spice @@ -1,8 +1,8 @@ * CDAC Simulation -.include "sscs-chipathon-sar-adc/gf180mcu-pdk/libraries/gf180mcu_fd_pr/latest/models/ngspice/design.ngspice" -.lib "sscs-chipathon-sar-adc/gf180mcu-pdk/libraries/gf180mcu_fd_pr/latest/models/ngspice/sm141064.ngspice" typical -.lib "sscs-chipathon-sar-adc/gf180mcu-pdk/libraries/gf180mcu_fd_pr/latest/models/ngspice/sm141064.ngspice" mimcap_typical +.include "globalfoundries-pdk-libs-gf180mcu_fd_pr/models/ngspice/design.ngspice" +.lib "globalfoundries-pdk-libs-gf180mcu_fd_pr/models/ngspice/sm141064.ngspice" typical +.lib "globalfoundries-pdk-libs-gf180mcu_fd_pr/models/ngspice/sm141064.ngspice" mimcap_typical .param width=10u