From 26300d6516e2c5b454d425c1f08ad61e7a27e1ac Mon Sep 17 00:00:00 2001 From: Mario Romero Date: Fri, 28 Apr 2023 03:02:21 +0000 Subject: [PATCH] Update 'spice/cdac.spice' --- spice/cdac.spice | 53 ++++++++++++++++++++++++++++-------------------- 1 file changed, 31 insertions(+), 22 deletions(-) diff --git a/spice/cdac.spice b/spice/cdac.spice index a299020..c5f0999 100644 --- a/spice/cdac.spice +++ b/spice/cdac.spice @@ -8,15 +8,21 @@ * Voltage sources definition .param vh=3.3 -.param timescale=0.1 +.param timescale=5m VCC ref 0 5 -VD1 d1 0 PULSE(0 {vh} {0*timescale} 1p 1p {11*timescale} {12*timescale}) -VD2 d2 0 PULSE(0 {vh} {1*timescale} 1p 1p {9*timescale} {12*timescale}) -VD3 d3 0 PULSE(0 {vh} {2*timescale} 1p 1p {7*timescale} {12*timescale}) -VD4 d4 0 PULSE(0 {vh} {3*timescale} 1p 1p {5*timescale} {12*timescale}) -VD5 d5 0 PULSE(0 {vh} {4*timescale} 1p 1p {3*timescale} {12*timescale}) -VD6 d6 0 PULSE(0 {vh} {5*timescale} 1p 1p {1*timescale} {12*timescale}) +VD1 d1 0 PULSE(0 {vh} {1*timescale} 1p 1p {23*timescale} {25*timescale}) +VD2 d2 0 PULSE(0 {vh} {2*timescale} 1p 1p {21*timescale} {25*timescale}) +VD3 d3 0 PULSE(0 {vh} {3*timescale} 1p 1p {19*timescale} {25*timescale}) +VD4 d4 0 PULSE(0 {vh} {4*timescale} 1p 1p {17*timescale} {25*timescale}) +VD5 d5 0 PULSE(0 {vh} {5*timescale} 1p 1p {15*timescale} {25*timescale}) +VD6 d6 0 PULSE(0 {vh} {6*timescale} 1p 1p {13*timescale} {25*timescale}) +VD7 d7 0 PULSE(0 {vh} {7*timescale} 1p 1p {11*timescale} {25*timescale}) +VD8 d8 0 PULSE(0 {vh} {8*timescale} 1p 1p {9*timescale} {25*timescale}) +VD9 d9 0 PULSE(0 {vh} {9*timescale} 1p 1p {7*timescale} {25*timescale}) +VD10 d10 0 PULSE(0 {vh} {10*timescale} 1p 1p {5*timescale} {25*timescale}) +VD11 d11 0 PULSE(0 {vh} {11*timescale} 1p 1p {3*timescale} {25*timescale}) +VD12 d12 0 PULSE(0 {vh} {12*timescale} 1p 1p {1*timescale} {25*timescale}) * cdac_line: Capacitor controlled by switch .subckt cdac_line in out ref_a ref_b c_width=5u c_length=5u @@ -26,26 +32,29 @@ XC1 sw_out out mim_1p5fF c_width=c_width c_length=c_length m=1 .ends cdac_line * Components -XC0 0 out mim_1p5fF c_width=5u c_length=5u m=1 -XD1 d1 out ref 0 cdac_line -XD2 d2 out ref 0 cdac_line -XD3 d3 out ref 0 cdac_line -XD4 d4 out ref 0 cdac_line -XD5 d5 out ref 0 cdac_line -XD6 d6 out ref 0 cdac_line -XD7 d7 out ref 0 cdac_line -XD8 d8 out ref 0 cdac_line -XD9 d9 out ref 0 cdac_line -XD10 d10 out ref 0 cdac_line -XD11 d11 out ref 0 cdac_line -XD12 d12 out ref 0 cdac_line +.param cu=10u +XC0 0 outl mim_1p5fF c_width={sqrt(1)*cu} c_length={sqrt(1)*cu} m=1 +XCA outl outr mim_1p5fF c_width={sqrt(1)*cu} c_length={sqrt(1)*cu} m=1 +RCA outl outr 100T +XD1 d1 outl ref 0 cdac_line c_width={sqrt(1)*cu} c_length={sqrt(1)*cu} +XD2 d2 outl ref 0 cdac_line c_width={sqrt(2)*cu} c_length={sqrt(2)*cu} +XD3 d3 outl ref 0 cdac_line c_width={sqrt(4)*cu} c_length={sqrt(4)*cu} +XD4 d4 outl ref 0 cdac_line c_width={sqrt(8)*cu} c_length={sqrt(8)*cu} +XD5 d5 outl ref 0 cdac_line c_width={sqrt(16)*cu} c_length={sqrt(16)*cu} +XD6 d6 outl ref 0 cdac_line c_width={sqrt(32)*cu} c_length={sqrt(32)*cu} +XD7 d7 outr ref 0 cdac_line c_width={sqrt(1)*cu} c_length={sqrt(1)*cu} +XD8 d8 outr ref 0 cdac_line c_width={sqrt(2)*cu} c_length={sqrt(2)*cu} +XD9 d9 outr ref 0 cdac_line c_width={sqrt(4)*cu} c_length={sqrt(4)*cu} +XD10 d10 outr ref 0 cdac_line c_width={sqrt(8)*cu} c_length={sqrt(8)*cu} +XD11 d11 outr ref 0 cdac_line c_width={sqrt(16)*cu} c_length={sqrt(16)*cu} +XD12 d12 outr ref 0 cdac_line c_width={sqrt(32)*cu} c_length={sqrt(32)*cu} .op .option post nomod .end .control -tran 1m 3.2 uic +tran 10u 100m uic set wr_singlescale -wrdata output.txt V(out) V(d1) V(d2) V(d3) V(d4) V(d5) V(d6) +wrdata output.txt V(outr) V(d1) V(d2) V(d3) V(d4) V(d5) V(d6) V(d7) V(d8) V(d9) V(d10) V(d11) V(d12) .endc \ No newline at end of file