diff --git a/spice/cdac.spice b/spice/cdac.spice
index be3159b..e2c09bf 100644
--- a/spice/cdac.spice
+++ b/spice/cdac.spice
@@ -4,32 +4,38 @@
 .lib "globalfoundries-pdk-libs-gf180mcu_fd_pr/models/ngspice/sm141064.ngspice" typical
 .lib "globalfoundries-pdk-libs-gf180mcu_fd_pr/models/ngspice/sm141064.ngspice" mimcap_typical
 
-.option method = gear
+*.option method = gear
 
 .param width=2.4u
 
 * Voltage sources definition
 .param vh=3.3
-.param timescale=5u
+.param timescale=1m
 
 VCC ref 0 3.3
-VD1 d1 0 PULSE({vh} 0 {1*timescale} 1p 1p {23*timescale} {25*timescale})
-VD2 d2 0 PULSE({vh} 0 {2*timescale} 1p 1p {21*timescale} {25*timescale})
-VD3 d3 0 PULSE({vh} 0 {3*timescale} 1p 1p {19*timescale} {25*timescale})
-VD4 d4 0 PULSE({vh} 0 {4*timescale} 1p 1p {17*timescale} {25*timescale})
-VD5 d5 0 PULSE({vh} 0 {5*timescale} 1p 1p {15*timescale} {25*timescale})
-VD6 d6 0 PULSE({vh} 0 {6*timescale} 1p 1p {13*timescale} {25*timescale})
-VD7 d7 0 PULSE({vh} 0 {7*timescale} 1p 1p {11*timescale} {25*timescale})
-VD8 d8 0 PULSE({vh} 0 {8*timescale} 1p 1p {9*timescale} {25*timescale})
-VD9 d9 0 PULSE({vh} 0 {9*timescale} 1p 1p {7*timescale} {25*timescale})
-VD10 d10 0 PULSE({vh} 0 {10*timescale} 1p 1p {5*timescale} {25*timescale})
-VD11 d11 0 PULSE({vh} 0 {11*timescale} 1p 1p {3*timescale} {25*timescale})
-VD12 d12 0 PULSE({vh} 0 {12*timescale} 1p 1p {1*timescale} {25*timescale})
+VD1 d1 0 PULSE(0 {vh} {1*timescale} 1p 1p {23*timescale} {25*timescale})
+VD2 d2 0 PULSE(0 {vh} {2*timescale} 1p 1p {21*timescale} {25*timescale})
+VD3 d3 0 PULSE(0 {vh} {3*timescale} 1p 1p {19*timescale} {25*timescale})
+VD4 d4 0 PULSE(0 {vh} {4*timescale} 1p 1p {17*timescale} {25*timescale})
+VD5 d5 0 PULSE(0 {vh} {5*timescale} 1p 1p {15*timescale} {25*timescale})
+VD6 d6 0 PULSE(0 {vh} {6*timescale} 1p 1p {13*timescale} {25*timescale})
+VD7 d7 0 PULSE(0 {vh} {7*timescale} 1p 1p {11*timescale} {25*timescale})
+VD8 d8 0 PULSE(0 {vh} {8*timescale} 1p 1p {9*timescale} {25*timescale})
+VD9 d9 0 PULSE(0 {vh} {9*timescale} 1p 1p {7*timescale} {25*timescale})
+VD10 d10 0 PULSE(0 {vh} {10*timescale} 1p 1p {5*timescale} {25*timescale})
+VD11 d11 0 PULSE(0 {vh} {11*timescale} 1p 1p {3*timescale} {25*timescale})
+VD12 d12 0 PULSE(0 {vh} {12*timescale} 1p 1p {1*timescale} {25*timescale})
+
+* inv: Inverter
+.subckt inv high low in out
+XQP out in high high pmos_3p3 w=width l=0.28u AD={width*0.24u} AS={width*0.24u} *PD={2*(width + 0.24u)} PS={2*(width + 0.24u)}
+XQN out in low  low  nmos_3p3 w=width l=0.28u AD={width*0.24u} AS={width*0.24u} *PD={2*(width + 0.24u)} PS={2*(width + 0.24u)}
+.ends inverter
 
 * cdac_line: Capacitor controlled by switch
 .subckt cdac_line in out ref_a ref_b c_width=5u c_length=5u
-XQP sw_out in ref_a sw_out  pmos_3p3 w=width l=0.28u AD={width*0.24u} AS={width*0.24u} *PD={2*(width + 0.24u)} PS={2*(width + 0.24u)}
-XQN sw_out in ref_b ref_b   nmos_3p3 w=width l=0.28u AD={width*0.24u} AS={width*0.24u} *PD={2*(width + 0.24u)} PS={2*(width + 0.24u)}
+XI1 ref_a ref_b in     in_neg inv
+XI2 ref_a ref_b in_neg sw_out inv
 XC1 sw_out out mim_1p5fF c_width=c_width c_length=c_length m=1
 .ends cdac_line
 
@@ -51,12 +57,14 @@ XD10 d10 outr ref 0 cdac_line c_width={sqrt(8)*cu}  c_length={sqrt(8)*cu}
 XD11 d11 outr ref 0 cdac_line c_width={sqrt(16)*cu} c_length={sqrt(16)*cu}
 XD12 d12 outr ref 0 cdac_line c_width={sqrt(32)*cu} c_length={sqrt(32)*cu}
 
+.include "param.spice"
+
 .op
 .option post nomod
 .end
 
 .control
-tran 10n 200u uic
+tran 10u 200m uic
 set wr_singlescale
 wrdata output.txt V(outr) V(d1) V(d2) V(d3) V(d4) V(d5) V(d6) V(d7) V(d8) V(d9) V(d10) V(d11) V(d12)
 .endc