From 7091945ed876c5f2f47958767be110db3479a272 Mon Sep 17 00:00:00 2001
From: Mario Romero <mario@1159.cl>
Date: Mon, 7 Aug 2023 19:18:08 +0000
Subject: [PATCH] Add Instruction Memory

---
 Instruction-Memory.md | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)
 create mode 100644 Instruction-Memory.md

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+# Instruction Memory
+
+> *Defined in [rtl/instr_memory.sv](https://git.1159.cl/Mario1159/RVSCC/src/branch/main/rtl/extend.sv)*
+
+<table>
+    <tr>
+        <th>Figure</th>
+        <th>Direction</th>
+        <th>Signal</th>
+    </tr>
+    <tr>
+        <td></td>
+        <td>Interface</td>
+        <td>instr_mem_if</td>
+    </tr>
+</table>
+
+The instruction memory is read only and the data can be specified using the `FILE_PATH` parameter. The file to read needs to be in the hexadecimal format provided by the `$readmemh` function of the SystemVerilog standard. Binary executables can be transformed to the hexadecimal format using `objcopy` or more convenient using the `rvscc_bin_to_verilog_mem_file` CMake function from [cmake/utils.cmake](https://git.1159.cl/Mario1159/RVSCC/src/branch/main/cmake/utils.cmake) that is being used when building the test or the sandbox project.