84 lines
2.3 KiB
Systemverilog
84 lines
2.3 KiB
Systemverilog
`include "timescale.sv"
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module cache_memory #(
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parameter int ADDR_SIZE = 32,
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parameter int NUM_SETS = 16,
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parameter int NUM_WAYS = 4,
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parameter int BLOCK_SIZE = 32
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) (
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input logic clk,
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input logic rst,
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input logic [$clog2(NUM_WAYS) - 1:0] write_way,
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input logic [$clog2(NUM_SETS) - 1:0] set,
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input logic [ADDR_SIZE - $clog2(NUM_SETS) - $clog2(BLOCK_SIZE / 4) - 1:0] tag,
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input logic write_enable,
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input logic [BLOCK_SIZE - 1:0] write_data,
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output logic [BLOCK_SIZE - 1:0] read_data,
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output logic [$clog2(NUM_WAYS) - 1:0] populate_way,
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output logic hit
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);
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localparam int NumBlockBytes = BLOCK_SIZE / 4;
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localparam int ByteOffsetSize = $clog2(NumBlockBytes);
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localparam int WaySize = $clog2(NUM_WAYS);
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localparam int SetSize = $clog2(NUM_SETS);
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localparam int TagSize = ADDR_SIZE - SetSize - ByteOffsetSize;
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logic [NUM_WAYS - 1:0] hits;
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logic [WaySize-1:0] way;
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logic [WaySize-1:0] read_way;
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priority_encoder #(.N(WaySize)) read_way_encoder (
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.data_in(hits),
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.data_out(read_way),
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.valid(hit)
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);
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always_comb begin
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if(write_enable)
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way = write_way;
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else
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way = read_way;
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end
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typedef struct packed {
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logic [BLOCK_SIZE - 1:0] data;
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logic [TagSize - 1:0] tag;
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logic valid;
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} cache_line_t;
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typedef cache_line_t [NUM_SETS - 1:0] cache_way;
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cache_way [NUM_WAYS - 1:0] ways;
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assign read_data = ways[way][set].data;
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always_ff @(posedge clk) begin
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if (rst) begin
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// Reset valid flags
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for (int i = 0; i < NUM_WAYS; i++) begin
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for (int j = 0; j < NUM_SETS; j++) begin
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ways[i][j].data <= BLOCK_SIZE'('dx);
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ways[i][j].tag <= TagSize'('dx);
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ways[i][j].valid <= 0;
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end
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end
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end else if (write_enable) begin
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ways[way][set].data <= write_data;
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ways[way][set].tag <= tag;
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ways[way][set].valid <= 1;
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end
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end
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logic [NUM_WAYS - 1:0] valid_flags;
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always_comb begin
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for (int i = 0; i < NUM_WAYS; i++) begin
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valid_flags[i] = ways[i][set].valid;
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hits[i] = ways[i][set].valid && (tag == ways[i][set].tag);
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end
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end
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priority_encoder #(.N(WaySize)) populate_way_encoder (
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.data_in(valid_flags),
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.data_out(populate_way),
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.valid('dz)
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);
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endmodule
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