RVSCC/rtl/RV32IDefs.sv
Mario1159 bb5f00d8dc
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Add register file test
2023-02-23 22:31:08 +00:00

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Systemverilog

package rv32i_defs;
typedef enum logic[2:0]{
SUM = 'b000,
SUB = 'b001,
OR = 'b011,
AND = 'b010,
SLT = 'b101
} alu_opcode;
typedef enum logic[6:0]{
STALL = 'b0000000,
REG_OPERATION = 'b0110011,
IMM_OPERATION = 'b0010011,
LOAD = 'b0000011,
STORE = 'b0100011,
BRANCH = 'b1100011,
JAL = 'b1101111,
JALR = 'b1100111,
LUI = 'b0110111,
AUIPC = 'b0010111} opcode_fmt;
endpackage