RVSCC/rtl/instr_memory.sv
Mario Romero 24a5622103
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Add 5 stage pipeline test and move timescale to include
2023-02-27 23:22:34 -03:00

25 lines
586 B
Systemverilog

`include "timescale.sv"
import rv32i_defs::*;
module instr_memory #(
parameter string FILE_PATH = "",
parameter int NUM_INSTR = 32
) (
instr_memory_if.mem instr_mem_if
);
// Number of bits referenced with one address
localparam int BlockSize = 8;
localparam int NumBlocks = NUM_INSTR * 4;
logic [BlockSize-1:0] mem[NumBlocks];
assign instr_mem_if.instr = {
mem[instr_mem_if.addr+'d0],
mem[instr_mem_if.addr+'d1],
mem[instr_mem_if.addr+'d2],
mem[instr_mem_if.addr+'d3]
};
initial $readmemh(FILE_PATH, mem);
endmodule