67 lines
1.8 KiB
CMake
67 lines
1.8 KiB
CMake
cmake_minimum_required(VERSION 3.10)
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function(rvscc_bin_to_verilog_mem_file)
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cmake_parse_arguments(RVSCC
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""
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"TARGET"
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""
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${ARGN}
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)
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add_custom_command(TARGET ${RVSCC_TARGET} POST_BUILD
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COMMAND ${CMAKE_OBJCOPY} -j .text
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-O verilog
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--verilog-data-width=1
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--reverse-bytes=4
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"$<TARGET_FILE:${RVSCC_TARGET}>" ${RVSCC_TARGET}.mem
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COMMENT "Invoking: Verilog Hexdump"
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)
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endfunction()
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function(rvscc_dissasemble)
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cmake_parse_arguments(RVSCC
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""
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"TARGET"
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""
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${ARGN}
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)
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add_custom_command(TARGET ${RVSCC_TARGET} POST_BUILD
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COMMAND ${CMAKE_OBJDUMP} -S "$<TARGET_FILE:${RVSCC_TARGET}>" > ${RVSCC_TARGET}.disasm
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COMMENT "Invoking: Disassemble"
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)
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endfunction()
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function(rvscc_add_test)
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cmake_parse_arguments(TEST
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""
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"NAME"
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"SOURCES"
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${ARGN}
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)
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message("Adding test ${TEST_NAME}")
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set(TEST_TARGET_NAME test-${TEST_NAME})
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add_executable(${TEST_TARGET_NAME} sim_individual_test.cpp)
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if ("${CMAKE_BUILD_TYPE}" EQUAL "Release")
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verilate(${TEST_TARGET_NAME}
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SOURCES ${TEST_SOURCES}
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SYSTEMC
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VERILATOR_ARGS --timing
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)
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else() # Debug
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verilate(${TEST_TARGET_NAME}
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SOURCES ${TEST_SOURCES}
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TRACE
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SYSTEMC
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VERILATOR_ARGS --timing
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)
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endif()
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set_property(TARGET ${TEST_TARGET_NAME} PROPERTY CXX_STANDARD ${SystemC_CXX_STANDARD})
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verilator_link_systemc(${TEST_TARGET_NAME})
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list(GET TEST_SOURCES 0 TEST_TOP_MODULE)
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get_filename_component(TEST_TOP_MODULE_NAME ${TEST_TOP_MODULE} NAME_WE)
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target_compile_definitions(${TEST_TARGET_NAME} PRIVATE
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TEST_HEADER="V${TEST_TOP_MODULE_NAME}.h"
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TEST_CLASS=V${TEST_TOP_MODULE_NAME}
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)
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add_test(NAME ${TEST_TARGET_NAME} COMMAND ${TEST_TARGET_NAME})
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endfunction()
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