13 lines
227 B
Systemverilog
13 lines
227 B
Systemverilog
`timescale 1ns / 1ps
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module Test_CPU();
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logic clk, reset;
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PipelinedCPU cpu(clk, reset);
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always #10 clk = ~clk;
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initial begin
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clk = 0;
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reset = 1;
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#100
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reset = 0;
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end
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endmodule
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