79 lines
1.9 KiB
Systemverilog
79 lines
1.9 KiB
Systemverilog
`include "timescale.sv"
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module two_way_lru_cache #(
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parameter int ADDR_SIZE = 32,
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parameter int NUM_SETS = 16,
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parameter int BLOCK_SIZE = 32
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) (
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input logic clk,
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input logic rst,
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input logic [ADDR_SIZE - 1:0] addr,
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input logic write_enable,
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input logic [BLOCK_SIZE - 1:0] write_data,
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output logic [BLOCK_SIZE - 1:0] read_data,
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output logic hit
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);
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localparam int NumWays = 2;
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localparam int NumBlockBytes = BLOCK_SIZE / 4;
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localparam int ByteOffsetSize = $clog2(NUM_BLOCK_BYTES);
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localparam int WaySize = $clog2(NUM_WAYS);
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localparam int SetSize = $clog2(NUM_SETS);
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localparam int TagSize = ADDR_SIZE - SET_SIZE - BYTE_OFFSET_SIZE;
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logic [NUM_WAYS - 1:0] valid_flags;
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logic [NUM_WAYS - 1:0] hits;
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logic [WAY_SIZE - 1:0] way;
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logic [SET_SIZE - 1:0] set;
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logic [TAG_SIZE - 1:0] tag;
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cache_memory #(
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.ADDR_SIZE (ADDR_SIZE),
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.NUM_SETS (NUM_SETS),
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.NUM_WAYS (NumWays),
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.BLOCK_SIZE(BLOCK_SIZE)
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) cache_memory (
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.clk(clk),
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.rst(rst),
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.way(way),
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.set(set),
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.tag(tag),
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.write_enable(write_enable),
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.write_data(write_data),
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.read_data(read_data),
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.hits(hits),
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.valid_flags(valid_flags)
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);
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two_way_lru_cru #(
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.ADDR_SIZE (ADDR_SIZE),
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.NUM_SETS (NUM_SETS),
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.BLOCK_SIZE
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) cache_replace_unit (
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.clk(clk),
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.rst(rst),
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.addr(addr),
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.replace(cru_enable),
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.preferred(replace_preferred_way)
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);
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cache_controller #(
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.ADDR_SIZE (ADDR_SIZE),
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.NUM_SETS (NUM_SETS),
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.NUM_WAYS (NUM_WAYS),
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.BLOCK_SIZE(BLOCK_SIZE)
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) cache_controller (
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.clk(clk),
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.addr(addr),
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.write_enable(write_enable),
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.replace_way(replace_preferred_way),
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.hits(hits),
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.valid_flags(valid_flags),
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.set(set),
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.tag(tag),
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.way(way),
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.hit(hit),
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.cru_enable(cru_enable)
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);
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endmodule
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