Mario1159/RVSCC
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RISC-V Simple Core Collection
3 Commits 3 Branches 0 Tags 356 KiB
SystemVerilog 79.3%
CMake 14.4%
Assembly 2.6%
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README.md First commit 2022-11-26 07:44:00 -03:00

README.md

5-Stage RISC-V Processor pipelined CPU with hazard detection