20 lines
453 B
Systemverilog
20 lines
453 B
Systemverilog
`timescale 1ns / 1ps
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// N = Bit width
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module InstructionMemory #(
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parameter int N = 32,
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parameter int N_INSTR = 32,
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parameter int BYTE_WIDTH = 8
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) (
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input logic [N-1:0] addr,
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output logic [N-1:0] instr
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);
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logic [BYTE_WIDTH-1:0] mem[N_INSTR*BYTE_WIDTH-1:0];
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always_comb begin
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instr = {mem[addr+'d0], mem[addr+'d1], mem[addr+'d2], mem[addr+'d3]};
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end
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initial $readmemh("sandbox.mem", mem);
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endmodule
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