54 lines
1.5 KiB
Systemverilog
54 lines
1.5 KiB
Systemverilog
`timescale 1ns / 1ps
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module HazardUnit (
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input logic rst,
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execute_pc_src,
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execute_result_src_0,
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memory_reg_write,
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writeback_reg_write,
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input logic [4:0] decode_rs_1,
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decode_rs_2,
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execute_rs_1,
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execute_rs_2,
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execute_rd,
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memory_rd,
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writeback_rd,
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output logic fetch_stall,
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decode_stall,
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decode_flush,
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execute_flush,
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output logic [1:0] execute_forward_a,
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execute_forward_b
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);
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logic lw_stall;
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always_comb begin
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if (rst) begin
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fetch_stall = 0;
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decode_stall = 0;
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decode_flush = 1;
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execute_flush = 1;
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execute_forward_a = 0;
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execute_forward_b = 0;
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end else begin
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if (((execute_rs_1 == memory_rd) & memory_reg_write) & (execute_rs_1 != 0))
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execute_forward_a = 'b10;
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else if (((execute_rs_1 == writeback_rd) & writeback_reg_write) & (execute_rs_1 != 0))
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execute_forward_a = 'b01;
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else execute_forward_a = 'b00;
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if (((execute_rs_2 == memory_rd) & memory_reg_write) & (execute_rs_2 != 0))
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execute_forward_b = 'b10;
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else if (((execute_rs_2 == writeback_rd) & writeback_reg_write) & (execute_rs_2 != 0))
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execute_forward_b = 'b01;
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else execute_forward_b = 'b00;
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lw_stall = execute_result_src_0 & ((decode_rs_1 == execute_rd) | (decode_rs_2 == execute_rd));
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fetch_stall = lw_stall;
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decode_stall = lw_stall;
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decode_flush = execute_pc_src;
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execute_flush = lw_stall | execute_pc_src;
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end
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end
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endmodule
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