49 lines
1016 B
Systemverilog
49 lines
1016 B
Systemverilog
`include "timescale.sv"
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import rv32i_defs::*;
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module test_two_way_lru_cache();
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logic clk, rst;
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data_memory_if mem_if(.clk(clk), .rst(rst));
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two_way_lru_cache DUT(
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.data_mem_if(mem_if)
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);
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localparam int ClockCycle = 2;
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always #(ClockCycle/2) clk = !clk;
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localparam int MemoryWriteRange = 64;
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logic [MemoryWriteRange-1:0][OperandSize-1:0] write_values;
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int start_addr;
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initial begin
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// Reset
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clk = 0;
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rst = 1;
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mem_if.write_enable = 0;
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#4;
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rst = 0;
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// Write to a range of values in memory
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mem_if.write_enable = 1;
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start_addr = $urandom;
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for (int i = 0; i < MemoryWriteRange; i++) begin
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mem_if.addr = 32'(start_addr + i * 4);
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write_values[i] = $urandom;
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mem_if.write_data = write_values[i];
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#2;
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end
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// Read and compare the same range of values
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mem_if.write_enable = 0;
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#4;
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for (int i = 0; i < MemoryWriteRange; i++) begin
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mem_if.addr = 32'(start_addr + i * 4);
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#2;
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end
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$finish;
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end
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endmodule
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