38 lines
762 B
Systemverilog
38 lines
762 B
Systemverilog
`include "timescale.sv"
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module test_single_cycle_core ();
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logic clk, rst;
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always #1 clk = ~clk;
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instr_memory_if instr_mem_if ();
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instr_memory #(
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.FILE_PATH("../fw/test/test-core.mem")
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) instr_mem (
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.instr_mem_if(instr_mem_if.mem)
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);
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data_memory_if data_mem_if (
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.clk(clk),
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.rst(rst)
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);
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data_memory #(.NUM_BLOCKS(128)) data_mem (.data_mem_if(data_mem_if.ram));
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single_cycle_datapath dut (
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.clk(clk),
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.rst(rst),
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.instr_mem_if(instr_mem_if.datapath),
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.data_mem_if(data_mem_if.datapath)
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);
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always @(posedge clk) data_mem_if.check_fw_test_core_assertions();
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initial begin
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clk = 0;
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rst = 1;
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#4;
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rst = 0;
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#1000;
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$error("Program execution timeout");
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end
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endmodule
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