16 lines
275 B
Systemverilog
16 lines
275 B
Systemverilog
`timescale 1ns / 1ps
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// N = Bit width
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module InstructionMemory #(
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parameter N = 32,
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parameter SIZE = 32
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)
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(
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input logic[N-1:0] addr,
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output logic[N-1:0] instr
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);
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logic[N-1:0] mem [SIZE-1:0];
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initial $readmemh("../build/program.hex", mem);
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endmodule
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