37 lines
712 B
Systemverilog
37 lines
712 B
Systemverilog
`timescale 1ns / 1ps
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module Test_DataMemory();
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logic clk, rst;
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logic[31:0] addr;
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logic write_enable;
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logic[31:0] write_data;
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logic[31:0] read_data;
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DataMemory #(
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.SIZE(16)
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) data_memory(
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clk,
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rst,
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addr,
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write_enable,
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write_data,
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read_data
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);
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always #1 clk = ~clk;
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initial begin
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clk = 0;
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rst = 1;
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write_enable = 0;
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#4;
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rst = 0;
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#1;
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write_enable = 1;
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for(int i = 0; i < 16; i++) begin
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addr = $urandom_range(15);
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write_data = $urandom();
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#2;
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end
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end
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endmodule
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