47 lines
946 B
Systemverilog
47 lines
946 B
Systemverilog
`timescale 1ns / 1ps
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module PipelinedControlUnit (
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input logic [6:0] opcode,
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input logic [2:0] funct_3,
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input logic [6:0] funct_7,
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output logic reg_write,
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output logic [1:0] result_src,
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output logic mem_write,
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output logic branch,
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output logic [2:0] alu_ctrl,
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output logic alu_src,
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output logic [1:0] imm_src
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);
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//logic branch, branch_result, branch_neg, jump;
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//assign pc_src = (branch & branch_result) | jump;
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/*
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always_comb begin
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case(branch_neg)
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'd0: branch_result = !zero;
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'd1: branch_result = zero;
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endcase
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end*/
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logic [1:0] alu_op;
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MainDecoder main_decoder (
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opcode,
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branch,
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jump,
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result_src,
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mem_write,
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alu_src,
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imm_src,
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reg_write,
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alu_op
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);
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ALUDecoder alu_decoder (
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opcode[5],
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funct_3,
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funct_7[5],
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alu_op,
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alu_ctrl,
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branch_neg
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);
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endmodule
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