28 lines
780 B
Systemverilog
28 lines
780 B
Systemverilog
`timescale 1ns / 1ps
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module DataMemory #(
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parameter N = 32,
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parameter SIZE = 32,
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parameter BYTE_WIDTH = 8)(
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input logic clk, rst,
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input logic[N-1:0] addr,
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input logic write_enable,
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input logic[N-1:0] write_data,
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output logic[N-1:0] read_data
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);
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logic[BYTE_WIDTH-1:0] mem[SIZE*BYTE_WIDTH-1:0];
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assign read_data = {mem[addr + 'd0],
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mem[addr + 'd1],
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mem[addr + 'd2],
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mem[addr + 'd3]};
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always_ff @(posedge clk) begin
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if (rst)
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mem = '{default: '0};
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else if (write_enable)
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{mem[addr + 'd0],
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mem[addr + 'd1],
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mem[addr + 'd2],
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mem[addr + 'd3]} <= write_data;
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end
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endmodule |