18 lines
499 B
Systemverilog
18 lines
499 B
Systemverilog
`timescale 1ns / 1ps
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module Extend
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(
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input logic[1:0] imm_src,
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input logic[31:7] instr,
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output logic[31:0] imm_ext
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);
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always_comb begin
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case(imm_src)
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'd0: imm_ext = {{20{instr[31]}}, instr[31:20]}; // Type I
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'd1: imm_ext = {{20{instr[31]}}, instr[31:25], instr[11:7]}; // Type S
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'd2: imm_ext = {{20{instr[31]}}, instr[7], instr[30:25], instr[11:8], 1'b0} ; // Type S
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default: imm_ext = 'dx;
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endcase
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end
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endmodule
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