43 lines
1.1 KiB
Systemverilog
43 lines
1.1 KiB
Systemverilog
`timescale 1ns / 1ps
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// N = Bit width
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module ALU #(parameter N = 32)
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(
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input logic[N-1:0] a,
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input logic[N-1:0] b,
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input logic[1:0] opcode,
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output logic[N-1:0] result,
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output logic[3:0] status
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);
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logic n, z, c, v;
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// Check if the signs of the operands are equal considering substraction sign simplification over the B operand
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logic opsign_comp = (a[N-1] == (b[N-1] ^ opcode[0]));
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// There is an overflow if the signs are equal and the result differ from the operation sign
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// The overflow flag only gets assign when the operation is either a sum or a substraction
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logic v_value = opsign_comp && (result != a[N-1]);
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always_comb begin
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case(opcode)
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2'd0: begin // Addition
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{c, result} = a + b;
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v = v_value;
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end
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2'd1: begin // Substraction
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{c, result} = a - b;
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v = v_value;
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end
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2'd2: begin // Or
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result = a | b;
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c = 1'b0;
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v = 1'b0;
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end
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2'd3: begin // And
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result = a & b;
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c = 1'b0;
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v = 1'b0;
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end
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endcase
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n = result[N-1];
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z = (result == '0);
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status = {n, z, c, v};
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end
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endmodule |