93 lines
2.1 KiB
Systemverilog
Executable File
93 lines
2.1 KiB
Systemverilog
Executable File
`include "timescale.sv"
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import rv32i_defs::*;
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module main_decoder (
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input logic [6:0] opcode,
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output logic branch,
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output logic jump,
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output logic [1:0] result_src,
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output logic mem_write,
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output logic alu_src,
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output logic [1:0] imm_src,
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output logic reg_write,
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output logic [1:0] alu_op
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);
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opcode_fmt_t opcode_enum;
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assign opcode_enum = opcode_fmt_t'(opcode);
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always_comb begin
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case (opcode)
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LOAD: begin // lw
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reg_write = 1;
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imm_src = 'b00;
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alu_src = 1;
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mem_write = 0;
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result_src = 'b01;
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branch = 0;
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alu_op = 'b00;
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jump = 0;
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end
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STORE: begin // sw
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reg_write = 0;
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imm_src = 'b01;
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alu_src = 1;
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mem_write = 1;
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result_src = 2'bx0; // xx?
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branch = 0;
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alu_op = 'b00;
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jump = 0;
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end
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REG_OPERATION: begin // r-type
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reg_write = 1;
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imm_src = 2'bxx;
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alu_src = 0;
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mem_write = 0;
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result_src = 'b00;
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branch = 0;
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alu_op = 'b10;
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jump = 0;
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end
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BRANCH: begin // b-type
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reg_write = 0;
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imm_src = 'b10;
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alu_src = 0;
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mem_write = 0;
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result_src = 2'bxx;
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branch = 1;
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alu_op = 'b01;
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jump = 0;
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end
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IMM_OPERATION: begin // i-type
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reg_write = 1;
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imm_src = 'b00;
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alu_src = 1;
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mem_write = 0;
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result_src = 'b00;
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branch = 0;
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alu_op = 'b10;
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jump = 0;
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end
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JAL: begin // jal
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reg_write = 1;
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imm_src = 'b11;
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alu_src = 1'bx;
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mem_write = 0;
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result_src = 'b10;
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branch = 0;
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alu_op = 2'bxx;
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jump = 1;
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end
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default: begin
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reg_write = 'b0;
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imm_src = 2'bxx;
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alu_src = 1'bx;
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mem_write = 'b0;
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result_src = 'b00;
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branch = 'b0;
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alu_op = 2'bxx;
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jump = 'b0;
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end
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endcase
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end
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endmodule
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