38 lines
993 B
Systemverilog
38 lines
993 B
Systemverilog
`include "timescale.sv"
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module two_way_lru_cru #(
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parameter int ADDR_SIZE = 32,
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parameter int NUM_SETS = 16,
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parameter int BLOCK_SIZE = 32
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) (
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input logic clk,
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input logic rst,
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input logic [ADDR_SIZE - 1:0] addr,
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input logic replace,
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output logic preferred
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);
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localparam int NumBlocksBytes = BLOCK_SIZE / 4;
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localparam int ByteOffsetSize = $clog2(NumBlocksBytes);
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localparam int SetSize = $clog2(NUM_SETS);
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localparam int TagSize = ADDR_SIZE - SetSize - ByteOffsetSize;
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typedef struct packed {
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logic [ByteOffsetSize - 1:0] byte_offset;
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logic [SetSize - 1:0] set;
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logic [TagSize - 1:0] tag;
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} cache_addr_t;
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cache_addr_t packed_addr;
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assign packed_addr = cache_addr_t'(addr);
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logic [NUM_SETS - 1:0] lru;
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assign preferred = lru[packed_addr.set];
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always_ff @(posedge clk) begin
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if (rst) lru[packed_addr.set] <= 0;
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else if (replace) begin
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lru[packed_addr.set] <= !lru[packed_addr.set];
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end
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end
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endmodule
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