51 lines
1.2 KiB
Systemverilog
51 lines
1.2 KiB
Systemverilog
`include "timescale.sv"
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import rv32i_defs::*;
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module alu (
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input logic [OperandSize-1:0] a,
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input logic [OperandSize-1:0] b,
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input alu_opcode_t operation,
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output logic [OperandSize-1:0] result,
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output logic [3:0] status
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);
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logic n, z, c, v;
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always_comb begin
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case (operation)
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SUM: begin
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{c, result} = a + b;
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v = (result[OperandSize-1] & !a[OperandSize-1] & !b[OperandSize-1]) |
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(!result[OperandSize-1] & a[OperandSize-1] & b[OperandSize-1]);
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end
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SUB: begin
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{c, result} = a - b;
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v = (result[OperandSize-1] & !a[OperandSize-1] & !b[OperandSize-1]) |
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(!result[OperandSize-1] & a[OperandSize-1] & !b[OperandSize-1]);
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end
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OR: begin
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result = a | b;
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c = 'b0;
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v = 'b0;
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end
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AND: begin
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result = a & b;
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c = 'b0;
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v = 'b0;
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end
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SLT: begin
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result = {31'd0, a < b};
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c = 'b0;
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v = 'b0;
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end
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default: begin
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result = 'dx;
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c = 1'bx;
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v = 1'bx;
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end
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endcase
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n = result[OperandSize-1];
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z = (result == '0);
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status = {n, z, c, v};
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end
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endmodule
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