96 lines
2.4 KiB
Systemverilog
Executable File
96 lines
2.4 KiB
Systemverilog
Executable File
`timescale 1ns / 1ps
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import rv32i_defs::*;
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module test_register_file ();
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logic clk, rst;
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logic [RegisterSize-1:0] addr_1, addr_2, addr_3;
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logic write_enable_3;
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logic [OperandSize-1:0] write_data_3;
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logic [OperandSize-1:0] read_data_1, read_data_2;
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register_file DUT (
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.clk(clk),
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.rst(rst),
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.addr_1(addr_1),
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.addr_2(addr_2),
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.addr_3(addr_3),
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.write_enable_3(write_enable_3),
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.write_data_3(write_data_3),
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.read_data_1(read_data_1),
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.read_data_2(read_data_2)
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);
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always #1 clk = ~clk;
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logic [NumRegisters-1:0][OperandSize-1:0] write_values;
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initial begin
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$dumpfile("regfile.vcd");
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$dumpvars;
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// Reset
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clk = 0;
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rst = 1;
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write_enable_3 = 0;
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#4;
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rst = 0;
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#1;
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// Write to all registers
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write_enable_3 = 1;
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for (int i = 0; i < NumRegisters; i++) begin
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addr_1 = 5'($urandom);
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addr_2 = 5'($urandom);
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addr_3 = i[4:0];
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write_values[i] = $urandom;
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write_data_3 = write_values[i];
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$display("%h", write_values[i]);
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#2;
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end
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// Read and compare the values stored in each register using addr_1
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write_enable_3 = 0;
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#4;
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for (int i = 0; i < NumRegisters; i++) begin
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addr_1 = i[4:0];
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addr_2 = 5'($urandom);
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addr_3 = 5'($urandom);
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#2;
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if (i == 0) begin
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assert (read_data_1 == 'd0)
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else $error("Read failed at register x0 using addr_1, value should stay at 0");
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end else begin
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assert (read_data_1 == write_values[i])
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else
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$error(
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"Read failed at register x%h using addr_1 %d, %d",
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addr_1,
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read_data_1,
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write_values[i]
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);
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end
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end
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// Read and compare the values stored in each register using addr_2
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write_enable_3 = 0;
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#4;
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for (int i = 0; i < NumRegisters; i++) begin
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addr_1 = 5'($urandom);
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addr_2 = i[4:0];
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addr_3 = 5'($urandom);
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#2;
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if (i == 0) begin
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assert (read_data_2 == 'd0)
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else $error("Read failed at register x0 using addr_2, value should stay at 0");
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end else begin
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assert (read_data_2 == write_values[i])
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else
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$error(
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"Read failed at register x%h using addr_2 %d, %d",
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addr_2,
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read_data_2,
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write_values[i]
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);
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end
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end
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$finish;
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end
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endmodule
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