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RVSCC
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RISC-V Simple Core Collection
rtl
system-verilog
13
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3
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0
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356
KiB
SystemVerilog
79.3%
CMake
14.4%
Assembly
2.6%
C++
2.1%
Dockerfile
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0.8%
4371f479d1
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Mario1159
4371f479d1
Update 'README.md'
2022-11-27 22:45:51 +00:00
program
Add C toolchain
2022-11-27 03:45:36 -03:00
src
Adapt different modules parameters
2022-11-27 03:34:18 -03:00
.gitignore
Ignore program build files
2022-11-27 03:43:43 -03:00
README.md
Update 'README.md'
2022-11-27 22:45:51 +00:00
README.md
5-Stage RISC-V pipelined processor with hazard detection