67 lines
1.7 KiB
Systemverilog
67 lines
1.7 KiB
Systemverilog
`include "timescale.sv"
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module cache_controller #(
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parameter int ADDR_SIZE = 32,
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parameter int NUM_SETS = 16,
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parameter int NUM_WAYS = 4,
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parameter int BLOCK_SIZE = 32
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) (
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input logic [ADDR_SIZE - 1:0] addr,
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input logic write_enable,
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input logic [$clog2(NUM_WAYS) - 1:0] replace_way,
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input logic [$clog2(NUM_WAYS) - 1:0] populate_way,
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input logic populated,
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output logic cru_enable,
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output logic [$clog2(NUM_WAYS) - 1:0] write_way,
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output logic [$clog2(NUM_SETS) - 1:0] set,
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output logic [ADDR_SIZE - $clog2(NUM_SETS) - $clog2(BLOCK_SIZE / 4) - 1:0] tag
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);
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localparam int NumBlockBytes = BLOCK_SIZE / 4;
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localparam int ByteOffsetSize = $clog2(NumBlockBytes);
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localparam int SetSize = $clog2(NUM_SETS);
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localparam int TagSize = ADDR_SIZE - SetSize - ByteOffsetSize;
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localparam int WaySize = $clog2(NUM_WAYS);
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typedef struct packed {
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logic [TagSize - 1:0] tag;
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logic [SetSize - 1:0] set;
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logic [ByteOffsetSize - 1:0] byte_offset;
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} cache_addr_t;
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typedef enum logic [1:0] {
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READ = 'b00,
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WRITE_POPULATE = 'b10,
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WRITE_REPLACE = 'b11
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} cache_state_t;
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cache_addr_t packed_addr;
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cache_state_t state;
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always_comb begin
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packed_addr = cache_addr_t'(addr);
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set = packed_addr.set;
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tag = packed_addr.tag;
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state = cache_state_t'{write_enable, populated};
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case (state)
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READ: begin
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cru_enable = 0;
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write_way = 'dx;
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end
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WRITE_POPULATE: begin
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cru_enable = 0;
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write_way = populate_way;
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end
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WRITE_REPLACE: begin
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cru_enable = 1;
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write_way = replace_way;
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end
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default: begin
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cru_enable = 0;
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write_way = 'dx;
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end
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endcase
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end
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endmodule
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