117 lines
2.8 KiB
Systemverilog
117 lines
2.8 KiB
Systemverilog
`include "timescale.sv"
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import rv32i_defs::*;
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module single_cycle_datapath (
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input logic clk,
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input logic rst,
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instr_memory_if.datapath instr_mem_if,
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data_memory_if.datapath data_mem_if
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);
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logic [InstructionSize-1:0] pc, pc_next;
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logic [OperandSize-1:0] imm_ext;
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logic [InstructionSize-1:0] pc_target;
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assign pc_target = imm_ext + pc;
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logic pc_src;
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always_comb begin
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case (pc_src)
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'd0: pc_next = pc + 'd4;
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'd1: pc_next = pc_target;
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default: pc_next = 'dx;
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endcase
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end
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always_ff @(posedge clk) begin
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if (rst) pc <= 'b0;
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else pc <= pc_next;
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end
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assign instr_mem_if.addr = instr_mem_if.AddrSize'(pc);
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logic reg_write;
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logic [OperandSize-1:0] read_data_1, read_data_2;
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logic [OperandSize-1:0] result;
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register_file register_file (
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.clk(clk),
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.rst(rst),
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.addr_1(instr_mem_if.instr[19:15]),
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.addr_2(instr_mem_if.instr[24:20]),
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.addr_3(instr_mem_if.instr[11:7]),
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.write_enable_3(reg_write),
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.write_data_3(result),
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.read_data_1(read_data_1),
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.read_data_2(read_data_2)
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);
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logic [1:0] result_src;
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logic [1:0] imm_src;
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logic [2:0] alu_ctrl;
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logic alu_src;
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logic alu_status_zero;
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logic jump;
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logic branch;
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logic branch_alu_neg;
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control_unit control_unit (
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.opcode(instr_mem_if.instr[6:0]),
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.funct_3(instr_mem_if.instr[14:12]),
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.funct_7(instr_mem_if.instr[31:25]),
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.result_src(result_src),
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.mem_write(data_mem_if.write_enable),
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.alu_ctrl(alu_ctrl),
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.alu_src(alu_src),
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.imm_src(imm_src),
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.reg_write(reg_write),
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.jump(jump),
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.branch(branch),
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.branch_alu_neg(branch_alu_neg)
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);
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jump_control jump_control (
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.jump(jump),
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.branch(branch),
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.branch_alu_neg(branch_alu_neg),
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.zero(alu_status_zero),
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.pc_src(pc_src)
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);
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imm_extend imm_extend (
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.imm_src(imm_src[1:0]),
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.instr (instr_mem_if.instr[31:7]),
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.imm_ext(imm_ext[31:0])
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);
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logic [OperandSize-1:0] src_b;
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always_comb begin
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case (alu_src)
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'd0: src_b = read_data_2;
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'd1: src_b = imm_ext;
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default: src_b = 'dx;
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endcase
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end
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logic [OperandSize-1:0] alu_result;
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logic [3:0] alu_status;
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assign alu_status_zero = alu_status[2];
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alu alu (
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.a(read_data_1),
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.b(src_b),
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.operation(alu_opcode_t'(alu_ctrl)),
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.result(alu_result),
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.status(alu_status)
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);
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assign data_mem_if.write_data = read_data_2;
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assign data_mem_if.addr = alu_result;
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always_comb begin
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case (result_src)
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'b00: result = alu_result;
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'b01: result = data_mem_if.read_data;
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'b10: result = pc + 'd4;
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'b11: result = 'dx;
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default: result = 'dx;
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endcase
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end
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endmodule
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