28 lines
571 B
Systemverilog
28 lines
571 B
Systemverilog
`include "timescale.sv"
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module rotate_cru#(
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parameter ADDR_SIZE = 32,
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parameter NUM_SETS = 16,
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parameter NUM_WAYS = 4,
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parameter BLOCK_SIZE = 32
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)(
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input logic clk, rst,
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input logic replace,
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output logic[LRU_INDEX_SIZE - 1:0] preferred
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);
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logic[LRU_INDEX_SIZE - 1:0] write_preference;
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always_comb begin
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preferred = write_preference;
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end
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always_ff @(posedge clk) begin
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if (rst)
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write_preference <= 0;
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else if(replace)
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write_preference += 1;
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end
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endmodule
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