36 lines
942 B
Systemverilog
36 lines
942 B
Systemverilog
`include "timescale.sv"
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import rv32i_defs::*;
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module register_file (
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input logic clk,
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input logic rst,
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input logic [RegisterSize-1:0] addr_1,
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input logic [RegisterSize-1:0] addr_2,
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input logic [RegisterSize-1:0] addr_3,
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input logic write_enable_3,
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input logic [OperandSize-1:0] write_data_3,
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output logic [OperandSize-1:0] read_data_1,
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output logic [OperandSize-1:0] read_data_2
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);
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logic [OperandSize-1:0] mem [NumRegisters-1:1];
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logic [OperandSize-1:0] zero;
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always_comb begin
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zero = 'd0;
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if (addr_1 == 'd0) read_data_1 = zero;
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else read_data_1 = mem[addr_1];
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if (addr_2 == 'd0) read_data_2 = zero;
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else read_data_2 = mem[addr_2];
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end
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always_ff @(posedge clk) begin
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if (rst) begin
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mem <= '{default: '0};
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mem[2] <= 'd255;
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end else if (write_enable_3) begin
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mem[addr_3] <= write_data_3;
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end
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end
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endmodule
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