RVSCC/rtl/instr_memory_if.sv
Mario Romero 24a5622103
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Add 5 stage pipeline test and move timescale to include
2023-02-27 23:22:34 -03:00

19 lines
406 B
Systemverilog

`include "timescale.sv"
import rv32i_defs::*;
interface instr_memory_if #(
parameter int NUM_INSTR = 32
);
localparam int AddrSize = $clog2(NUM_INSTR) * 4;
logic [AddrSize-1:0] addr;
logic [InstructionSize-1:0] instr;
modport mem(input addr, output instr);
modport datapath(input instr, output addr);
function static void next_instr();
addr = addr + 'd4;
endfunction
endinterface