93 lines
2.2 KiB
Systemverilog
93 lines
2.2 KiB
Systemverilog
`include "timescale.sv"
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module cache_controller #(
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parameter int ADDR_SIZE = 32,
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parameter int NUM_SETS = 16,
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parameter int NUM_WAYS = 4,
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parameter int BLOCK_SIZE = 32
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) (
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input logic clk,
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input logic [ADDR_SIZE - 1:0] addr,
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input logic write_enable,
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input logic replace_way,
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input logic [NUM_WAYS - 1:0] hits,
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input logic [NUM_WAYS - 1:0] valid_flags,
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output logic [SetSize - 1:0] set,
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output logic [TagSize - 1:0] tag,
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output logic [WaySize - 1:0] way,
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output logic hit,
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output logic cru_enable
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);
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localparam int NumBlockBytes = BLOCK_SIZE / 4;
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localparam int ByteOffsetSize = $clog2(NumBlockBytes);
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localparam int SetSize = $clog2(NUM_SETS);
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localparam int TagSize = ADDR_SIZE - SetSize - ByteOffsetSize;
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localparam int WaySize = $clog2(NUM_WAYS);
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typedef struct packed {
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logic [ByteOffsetSize - 1:0] byte_offset;
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logic [SetSize - 1:0] set;
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logic [TagSize - 1:0] tag;
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} cache_addr_t;
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typedef enum logic [1:0] {
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READ = 'b00,
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WRITE_UNVALID = 'b10,
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REPLACE = 'b11
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} cache_state_t;
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cache_addr packed_addr;
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cache_state_t state;
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logic [WaySize - 1:0] valid_encode, next_unvalid_way;
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PriorityEncoder #(
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.N(WaySize)
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) valid_flags_encoder (
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.data_in(valid_flags),
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.data_out(valid_encode),
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.valid(valid_flags_encoder_valid)
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);
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PriorityEncoder #(
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.N(WaySize)
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) read_way_encoder (
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.data_in(hits),
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.data_out(read_way),
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.valid(read_way_encoder_valid)
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);
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logic valid;
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always_comb begin
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packed_addr = cache_addr'(addr);
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set = packed_addr.set;
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tag = packed_addr.tag;
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hit = |hits;
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valid = &valid_flags;
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state = cache_state_t'{write_enable, valid};
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case (state)
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READ: begin
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cru_enable = 0;
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if (read_way_encoder_valid) way = read_way;
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else way = 'd0;
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end
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WRITE_UNVALID: begin
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cru_enable = 0;
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way = next_unvalid_way;
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end
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REPLACE: begin
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cru_enable = 1;
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way = replace_way;
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end
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default: begin
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cru_enable = 0;
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way = 'dx;
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end
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endcase
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if (valid_flags_encoder_valid) next_unvalid_way = valid_encode + 'd1;
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else next_unvalid_way = 'd0;
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end
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endmodule
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