38 lines
1.0 KiB
Systemverilog
38 lines
1.0 KiB
Systemverilog
`include "timescale.sv"
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module two_way_lru_cru #(
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parameter ADDR_SIZE = 32,
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parameter NUM_SETS = 16,
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parameter BLOCK_SIZE = 32
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) (
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input logic clk, rst,
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input logic[ADDR_SIZE - 1:0] addr,
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input logic replace,
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output logic preferred
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);
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localparam NUM_BLOCK_BYTES = BLOCK_SIZE / 4;
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localparam BYTE_OFFSET_SIZE = $clog2(NUM_BLOCK_BYTES);
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localparam SET_SIZE = $clog2(NUM_SETS);
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localparam TAG_SIZE = ADDR_SIZE - SET_SIZE - BYTE_OFFSET_SIZE;
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typedef struct packed {
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logic[BYTE_OFFSET_SIZE - 1:0] byte_offset;
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logic[SET_SIZE - 1:0] set;
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logic[TAG_SIZE - 1:0] tag;
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} cache_addr;
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cache_addr packed_addr;
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assign packed_addr = cache_addr'(addr);
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logic[NUM_SETS - 1:0] lru;
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assign preferred = lru[packed_addr.set];
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always_ff @(posedge clk) begin
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if (rst)
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lru[packed_addr.set] <= 0;
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else if (replace) begin
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lru[packed_addr.set] <= !lru[packed_addr.set];
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end
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end
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endmodule
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