31 lines
659 B
Systemverilog
31 lines
659 B
Systemverilog
`include "timescale.sv"
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package rv32i_defs;
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// Sizes in bits
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localparam int OperandSize = 32;
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localparam int InstructionSize = 32;
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localparam int NumRegisters = 32;
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localparam int RegisterSize = $clog2(NumRegisters);
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typedef enum logic [2:0] {
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SUM = 'b000,
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SUB = 'b001,
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OR = 'b011,
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AND = 'b010,
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SLT = 'b101
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} alu_opcode_t;
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typedef enum logic [6:0] {
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STALL = 'b0000000,
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REG_OPERATION = 'b0110011,
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IMM_OPERATION = 'b0010011,
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LOAD = 'b0000011,
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STORE = 'b0100011,
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BRANCH = 'b1100011,
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JAL = 'b1101111,
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JALR = 'b1100111,
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LUI = 'b0110111,
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AUIPC = 'b0010111
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} opcode_fmt_t;
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endpackage
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