39 lines
1.1 KiB
Systemverilog
39 lines
1.1 KiB
Systemverilog
`include "timescale.sv"
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interface data_memory_if #(
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parameter int ADDR_SIZE = 32,
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parameter int DATA_SIZE = 32
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) (
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input logic clk,
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input logic rst
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);
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logic [ADDR_SIZE-1:0] addr;
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logic write_enable;
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logic [DATA_SIZE-1:0] write_data;
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logic [DATA_SIZE-1:0] read_data;
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logic hit;
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logic ready;
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modport datapath(input read_data, output addr, write_enable, write_data);
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modport ram(input clk, rst, addr, write_enable, write_data, output read_data);
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modport cache(input clk, rst, addr, write_enable, write_data, output read_data, hit);
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modport test(input read_data, write_enable, write_data);
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/*
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* Test assertion that should be used against test-core.s firmware.
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* This function checks if the results in data memory are the expected.
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* Must be called each clock cycle.
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*/
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function static void check_fw_test_core_assertions();
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if (write_enable) begin
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if (addr == 'd100 && write_data == 'd25) begin
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$finish;
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end else
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assert (addr == 'd96)
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else $error("Unexpected write address in test-core program");
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$finish;
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end
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endfunction
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endinterface
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