22 lines
651 B
Systemverilog
22 lines
651 B
Systemverilog
`timescale 1ns / 1ps
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module Test_PriorityEncoder();
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logic[7:0] data_in;
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logic[2:0] data_out;
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PriorityEncoder#(.N(3)) encoder(data_in, data_out);
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initial begin
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data_in = 'b00000001;
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for (int i = 0; i < 8; i++) begin
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assert (data_out == i + 1) else $error("[One-hot] Failed at " + i);
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#1
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data_in = data_in << 'd1;
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end
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#1
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data_in = 'b00101111;
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assert (data_out == 'd5) else $error("[Manual entry] Failed at " + 5);
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#1
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data_in = 'b10101010;
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assert (data_out == 'd7) else $error("[Manual entry] Failed at " + 7);
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end
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endmodule
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