65 lines
1.3 KiB
Systemverilog
65 lines
1.3 KiB
Systemverilog
`include "timescale.sv"
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module test_cache_memory ();
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logic clk;
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logic rst;
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logic [dut.WaySize-1:0] write_way;
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logic [dut.SetSize-1:0] set;
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logic [dut.TagSize-1:0] tag;
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logic write_enable;
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logic [31:0] write_data;
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logic [31:0] read_data;
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logic read_valid;
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logic [dut.WaySize-1:0] populate_way;
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cache_memory #(
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.ADDR_SIZE (32),
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.NUM_SETS (4),
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.NUM_WAYS (2),
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.BLOCK_SIZE(32)
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) dut (
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.clk(clk),
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.rst(rst),
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.write_way(write_way),
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.set(set),
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.tag(tag),
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.write_enable(write_enable),
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.write_data(write_data),
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.read_data(read_data),
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.read_valid(read_valid),
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.populate_way(populate_way)
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);
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localparam int ClockCycle = 2;
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always #(ClockCycle/2) clk = !clk;
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logic [31:0] write_value;
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initial begin
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clk = 0;
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rst = 1;
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#ClockCycle;
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rst = 0;
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write_way = 0;
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set = 0;
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tag = 27'($urandom);
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write_enable = 1;
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write_value = $urandom;
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write_data = write_value;
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#ClockCycle;
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write_enable = 0;
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tag += 1;
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#1;
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assert (read_valid == 0)
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else $error("Valid flags does not match");
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#ClockCycle;
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tag -= 1;
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#1;
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assert (read_valid == 1)
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else $error("Valid flags does not match");
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$finish;
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end
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endmodule
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