66 lines
1.6 KiB
Systemverilog
Executable File
66 lines
1.6 KiB
Systemverilog
Executable File
`timescale 1ns / 1ps
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import rv32i_defs::*;
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module test_data_memory ();
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localparam int NumInstr = 64;
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// Each block is a byte
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localparam int MemoryBlockSize = 8;
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// Each instruction address have 4 bytes
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localparam int NumMemoryBlocks = NumInstr * 4;
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localparam int AddrSize = $clog2(NumMemoryBlocks);
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logic clk, rst;
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data_memory_if #(
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.ADDR_SIZE(AddrSize),
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.DATA_SIZE(OperandSize)
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) mem_if (
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.clk(clk),
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.rst(rst)
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);
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data_memory #(
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.BLOCK_SIZE(MemoryBlockSize),
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.NUM_BLOCKS(NumMemoryBlocks)
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) dut (
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.data_mem_if(mem_if)
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);
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always #1 clk = ~clk;
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localparam int MemoryWriteRange = 16;
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logic [MemoryWriteRange-1:0][OperandSize-1:0] write_values;
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int start_addr;
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initial begin
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// Reset
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clk = 0;
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rst = 1;
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mem_if.write_enable = 0;
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#4;
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rst = 0;
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#1;
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// Write to a range of values in memory
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mem_if.write_enable = 1;
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start_addr = $urandom;
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for (int i = 0; i < MemoryWriteRange; i++) begin
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mem_if.addr = AddrSize'(start_addr + i * 4);
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write_values[i] = $urandom;
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mem_if.write_data = write_values[i];
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#2;
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end
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// Read and compare the same range of values
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mem_if.write_enable = 0;
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#4;
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for (int i = 0; i < MemoryWriteRange; i++) begin
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$display(start_addr, i, AddrSize);
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mem_if.addr = AddrSize'(start_addr + i * 4);
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#1;
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assert (mem_if.read_data == write_values[i])
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else $error("Read failed at address %h", mem_if.addr);
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#1;
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end
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$finish;
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end
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endmodule
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