76 lines
1.9 KiB
Systemverilog
Executable File
76 lines
1.9 KiB
Systemverilog
Executable File
`include "timescale.sv"
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module two_way_lru_cache #(
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parameter int ADDR_SIZE = 32,
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parameter int NUM_SETS = 16,
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parameter int BLOCK_SIZE = 32
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) (
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data_memory_if.cache data_mem_if
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);
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localparam int NumWays = 2;
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localparam int NumBlockBytes = BLOCK_SIZE / 4;
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localparam int ByteOffsetSize = $clog2(NumBlockBytes);
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localparam int WaySize = $clog2(NumWays);
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localparam int SetSize = $clog2(NUM_SETS);
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localparam int TagSize = ADDR_SIZE - SetSize - ByteOffsetSize;
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logic [$clog2(NumWays) - 1:0] populate_way;
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logic read_valid;
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logic [WaySize - 1:0] way;
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logic [SetSize - 1:0] xset;
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logic [TagSize - 1:0] tag;
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logic write_way;
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logic populated;
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cache_memory #(
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.ADDR_SIZE (ADDR_SIZE),
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.NUM_SETS (NUM_SETS),
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.NUM_WAYS (NumWays),
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.BLOCK_SIZE(BLOCK_SIZE)
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) cache_memory (
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.clk(data_mem_if.clk),
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.rst(data_mem_if.rst),
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.write_way(write_way),
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.set(xset),
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.tag(tag),
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.write_enable(data_mem_if.write_enable),
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.write_data(data_mem_if.write_data),
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.read_data(data_mem_if.read_data),
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.populate_way(populate_way),
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.populated(populated),
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.hit(data_mem_if.hit)
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);
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logic cru_enable;
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logic replace_preferred_way;
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two_way_lru_cru #(
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.ADDR_SIZE (ADDR_SIZE),
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.NUM_SETS (NUM_SETS),
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.BLOCK_SIZE(BLOCK_SIZE)
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) cache_replace_unit (
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.clk(data_mem_if.clk),
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.rst(data_mem_if.rst),
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.addr(data_mem_if.addr),
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.replace(cru_enable),
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.preferred(replace_preferred_way)
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);
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cache_controller #(
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.ADDR_SIZE (ADDR_SIZE),
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.NUM_SETS (NUM_SETS),
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.NUM_WAYS (NumWays),
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.BLOCK_SIZE(BLOCK_SIZE)
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) cache_controller (
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.addr(data_mem_if.addr),
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.write_enable(data_mem_if.write_enable),
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.replace_way(replace_preferred_way),
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.populate_way(populate_way),
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.populated(populated),
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.cru_enable(cru_enable),
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.write_way(write_way),
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.set(xset),
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.tag(tag)
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);
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endmodule
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