37 lines
846 B
Systemverilog
Executable File
37 lines
846 B
Systemverilog
Executable File
`include "timescale.sv"
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module pipelined_control_unit (
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input logic [6:0] opcode,
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input logic [2:0] funct_3,
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input logic [6:0] funct_7,
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output logic reg_write,
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output logic [1:0] result_src,
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output logic mem_write,
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output logic branch,
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output logic [2:0] alu_ctrl,
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output logic alu_src,
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output logic [1:0] imm_src
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);
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logic [1:0] alu_op;
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main_decoder main_decoder (
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.opcode(opcode),
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.branch(branch),
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.jump(jump),
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.result_src(result_src),
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.mem_write(mem_write),
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.alu_src(alu_src),
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.imm_src(imm_src),
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.reg_write(reg_write),
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.alu_op(alu_op)
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);
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alu_decoder alu_decoder (
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.opcode(opcode[5]),
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.funct_3(funct_3),
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.funct_7_5(funct_7[5]),
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.alu_op(alu_op),
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.alu_ctrl(alu_ctrl),
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.branch_neg(branch_neg)
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);
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endmodule
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