29 lines
730 B
Systemverilog
Executable File
29 lines
730 B
Systemverilog
Executable File
`include "timescale.sv"
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import rv32i_defs::*;
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module data_memory #(
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parameter int BLOCK_SIZE = 8,
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parameter int NUM_BLOCKS = 32
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) (
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data_memory_if.ram data_mem_if
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);
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logic [NUM_BLOCKS-1:0][BLOCK_SIZE-1:0] mem;
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assign data_mem_if.read_data = {
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mem[data_mem_if.addr+'d3],
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mem[data_mem_if.addr+'d2],
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mem[data_mem_if.addr+'d1],
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mem[data_mem_if.addr+'d0]
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};
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always_ff @(posedge data_mem_if.clk) begin
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if (data_mem_if.rst) mem <= '{default: '0};
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else if (data_mem_if.write_enable)
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{mem[data_mem_if.addr+'d3],
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mem[data_mem_if.addr+'d2],
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mem[data_mem_if.addr+'d1],
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mem[data_mem_if.addr+'d0]} <= data_mem_if.write_data;
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end
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endmodule
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