Add single cycle test and fix 'and' & 'or' instructions

rtl/alu_decoder.sv

@@ -49,11 +49,11 @@ module alu_decoder(
         branch_neg = 1'dx;
       end
       'b10110??: begin
-        alu_ctrl   = 3'b000;  // or
+        alu_ctrl   = 3'b011;  // or
         branch_neg = 1'dx;
       end
       'b10111??: begin
-        alu_ctrl   = 3'b000;  // and
+        alu_ctrl   = 3'b010;  // and
         branch_neg = 1'dx;
       end
       default: begin

rtl/single_cycle_datapath.sv

@@ -94,7 +94,7 @@ module single_cycle_datapath (
   alu alu (
       .a(read_data_1),
       .b(src_b),
-      .operation(alu_ctrl),
+      .operation(alu_opcode_t'(alu_ctrl)),
       .result(alu_result),
       .status(alu_status)
   );

test/test_instr_memory.sv

@@ -11,7 +11,7 @@ module test_instr_memory ();
   logic [AddrSize-1:0] addr;
   logic [InstructionSize-1:0] instr;
 
-  instr_memory_if #(.NUM_INSTR(NumInstr)) dut_if;
+  instr_memory_if #(.NUM_INSTR(NumInstr)) dut_if();
 
   instr_memory #(
       .FILE_PATH(Path),

test/test_single_cycle_core.sv

@@ -4,14 +4,14 @@ module test_single_cycle_core ();
   logic clk, rst;
   always #1 clk = ~clk;
 
-  instr_memory_if instr_mem_if;
-  instr_memory #(.FILE_PATH("../fw/test/test-core.mem")) instr_mem (instr_mem_if.mem);
+  instr_memory_if instr_mem_if();
+  instr_memory #(.FILE_PATH("test-core.mem")) instr_mem (.instr_mem_if(instr_mem_if.mem));
 
   data_memory_if data_mem_if (
       .clk(clk),
       .rst(rst)
   );
-  data_memory data_mem (.data_mem_if(data_mem_if.ram));
+  data_memory #(.NUM_BLOCKS(128)) data_mem (.data_mem_if(data_mem_if.ram));
 
   single_cycle_datapath dut (
       .clk(clk),
@@ -19,6 +19,15 @@ module test_single_cycle_core ();
       .instr_mem_if(instr_mem_if.datapath),
       .data_mem_if(data_mem_if.datapath)
   );
+  
+  always @(posedge clk) begin
+    if (data_mem_if.write_enable) begin
+        if(data_mem_if.addr == 'd100 && data_mem_if.write_data == 'd25) begin
+            $finish;
+        end else if (data_mem_if.addr != 'd96) // assert
+            $finish;
+    end
+  end
 
   initial begin
     $dumpfile("single_cycle.vcd");
@@ -27,7 +36,8 @@ module test_single_cycle_core ();
     rst = 1;
     #4;
     rst = 0;
-    #100;
+    #1000;
+    $display("Hello world");
     $finish;
   end
 endmodule